1. Field of the Invention
The present invention relates to a master slice type integrated circuit, and more specifically to such a master slice type integrated circuit of the gate array structure including a plurality of output buffers.
2. Description of Related Art
In the prior art, the master slice type integrated circuits have included for example a unitary circuit as shown in FIG. 1. In the shown circuit, an input signal Vi is supplied through an input buffer 10 to an internal macrocell (or macrogate) 12. In this specification, the term "macrocell" is used to mean one definite or consolidated function unit, which can be formed of one or more basic logic units or cells such as NOT, AND, OR, NAND, NOR etc, or a combination of basic logic cells. In the shown example, macrocell 12 is composed of an inverter 12A connected at its input to an output of the input buffer 10 and a two-input NAND gate 12B having a first input connected to an output of the inverter 12A and a second input connected to receive a suitable signal (not shown) so that a given processing can be performed. An output of the macrocell 12 (for example an output of the NAND gate 12B) is directly connected to an output buffer 14, which simply functions to supply the output of the macrocell 12 as an output signal Vo to an external after a delay time inherent to the output buffer 14.
In the master slice type integrated circuits, however, it is in some cases desired to cause a number of unitary circuits (macrocells) to have the same delay time between an input terminal and an output terminal. In other cases, it is required to shift the timing of the output signal of adjacent unitary circuits from each other.
On the other hand, the conventional master slice type integrated circuits have been designed by use of a CAD (computer aided design) tool, so that locations of respective macrocells as well as wiring between macrocells are automatically designed. As a result, the delay time of each unitary circuit (macrocell) has been fixed and therefore a desired delay time could not necessarily have been obtained.
Therefore, in order to cause some number of selected unitary circuits (macrocells) to have the same delay time between an input terminal and an output terminal, it is necessary for a person to perform a manual additional design modification for changing the locations and the wirings of all macrocells which are required to have the same delay time.
Furthermore, if a plurality of output buffers located adjacent to one another change their output signals at substantially the same timing, a power supply voltage and a ground potential are influenced by charge and discharge currents at output terminals of those output buffers, with the result that there would be a concern for malfunction of circuits. To prevent the malfunction, it is preferred to shift the output signal timings of adjacent output buffers little by little. For this purpose, however, the conventional master slice type integrated circuits also are required to manually add a number of gates before the output buffers or to change the internal wiring of the integrated circuit since the output buffers themselves have no function for controlling the delay time.
As mentioned above, the conventional master slice type integrated circuits have been such that an output of each internal macrocell is directly connected to an associated output buffer, and therefore, each unitary circuit composed of the macrocell has a fixed signal delay time between an input terminal and an output terminal. As a result, if it is necessary to adjust the delay time between an input terminal and an output terminal, a manual modification has been required at a stage of design for changing the locations and the wirings of the macrocells concerned and for adding a required number of gates. Accordingly, the design time for the integrated circuit design will be inevitably increased. In addition, since it was not possible to adjust the delay time and to compensate the dispersion of property caused by a manufacturing process, applications of finished products have been limited.